Architectural Power Management for BatteryLifetime Optimization in Portable Systems

For portable computing devices, maximizing battery lifetime or performing maximum possible operations per recharge is a primary objective. Various voltage and frequency scaling techniques are being used in commercial devices. This work considers the role of energy source, i.e., battery, in the optimization of a portable system. We introduce battery lifetime in number of clock cycles as an optimization metric. In addition the energy consumed by the system, battery lifetime also depends upon the battery efficiency, which may degrade as the power consumption increases. We examine power reduction techniques for a processor such as frequency scaling, i.e., clock slowdown (CSD) and instruction slowdown (ISD) from a battery efficiency viewpoint and estimate battery lifetime expressed in number of operational cycles. In case of ISD, implemented with the help of NOPs, we demonstrate that the lifetime for a given size of battery might be optimum at a slowdown factor around 2 to 3. The battery lifetime improvement requires reduced power dissipation coupled with prolonged execution time and, surprisingly, sometimes even increased energy consumption. With architecture level modifications, such as instruction slowdown, battery lifetime increase of 20% is realized.